diff --git a/tmp/ynl_build-tmp.ATJZN4/old-code/dpll-user.c b/tmp/ynl_build-tmp.ATJZN4/new-code/dpll-user.c
index c65a56e25aa1..5b3091e75661 100644
--- a/tmp/ynl_build-tmp.ATJZN4/old-code/dpll-user.c
+++ b/tmp/ynl_build-tmp.ATJZN4/new-code/dpll-user.c
@@ -203,6 +203,7 @@ const struct ynl_policy_attr dpll_pin_parent_device_policy[DPLL_A_PIN_MAX + 1] =
 	[DPLL_A_PIN_STATE] = { .name = "state", .type = YNL_PT_U32, },
 	[DPLL_A_PIN_OPERSTATE] = { .name = "operstate", .type = YNL_PT_U32, },
 	[DPLL_A_PIN_PHASE_OFFSET] = { .name = "phase-offset", .type = YNL_PT_U64, },
+	[DPLL_A_PIN_FRACTIONAL_FREQUENCY_OFFSET_PPT] = { .name = "fractional-frequency-offset-ppt", .type = YNL_PT_UINT, },
 };
 
 const struct ynl_policy_nest dpll_pin_parent_device_nest = {
@@ -344,6 +345,8 @@ int dpll_pin_parent_device_put(struct nlmsghdr *nlh, unsigned int attr_type,
 		ynl_attr_put_u32(nlh, DPLL_A_PIN_OPERSTATE, obj->operstate);
 	if (obj->_present.phase_offset)
 		ynl_attr_put_s64(nlh, DPLL_A_PIN_PHASE_OFFSET, obj->phase_offset);
+	if (obj->_present.fractional_frequency_offset_ppt)
+		ynl_attr_put_sint(nlh, DPLL_A_PIN_FRACTIONAL_FREQUENCY_OFFSET_PPT, obj->fractional_frequency_offset_ppt);
 	ynl_attr_nest_end(nlh, nest);
 
 	return 0;
@@ -388,6 +391,11 @@ int dpll_pin_parent_device_parse(struct ynl_parse_arg *yarg,
 				return YNL_PARSE_CB_ERROR;
 			dst->_present.phase_offset = 1;
 			dst->phase_offset = ynl_attr_get_s64(attr);
+		} else if (type == DPLL_A_PIN_FRACTIONAL_FREQUENCY_OFFSET_PPT) {
+			if (ynl_attr_validate(yarg, attr))
+				return YNL_PARSE_CB_ERROR;
+			dst->_present.fractional_frequency_offset_ppt = 1;
+			dst->fractional_frequency_offset_ppt = ynl_attr_get_sint(attr);
 		}
 	}
 
@@ -1015,11 +1023,6 @@ int dpll_pin_get_rsp_parse(const struct nlmsghdr *nlh,
 				return YNL_PARSE_CB_ERROR;
 			dst->_present.fractional_frequency_offset = 1;
 			dst->fractional_frequency_offset = ynl_attr_get_sint(attr);
-		} else if (type == DPLL_A_PIN_FRACTIONAL_FREQUENCY_OFFSET_PPT) {
-			if (ynl_attr_validate(yarg, attr))
-				return YNL_PARSE_CB_ERROR;
-			dst->_present.fractional_frequency_offset_ppt = 1;
-			dst->fractional_frequency_offset_ppt = ynl_attr_get_sint(attr);
 		} else if (type == DPLL_A_PIN_ESYNC_FREQUENCY) {
 			if (ynl_attr_validate(yarg, attr))
 				return YNL_PARSE_CB_ERROR;
diff --git a/tmp/ynl_build-tmp.ATJZN4/old-code/dpll-user.h b/tmp/ynl_build-tmp.ATJZN4/new-code/dpll-user.h
index 5123250e04b3..3d1a2652466b 100644
--- a/tmp/ynl_build-tmp.ATJZN4/old-code/dpll-user.h
+++ b/tmp/ynl_build-tmp.ATJZN4/new-code/dpll-user.h
@@ -49,6 +49,7 @@ struct dpll_pin_parent_device {
 		__u32 state:1;
 		__u32 operstate:1;
 		__u32 phase_offset:1;
+		__u32 fractional_frequency_offset_ppt:1;
 	} _present;
 
 	__u32 parent_id;
@@ -57,6 +58,7 @@ struct dpll_pin_parent_device {
 	enum dpll_pin_state state;
 	enum dpll_pin_operstate operstate;
 	__s64 phase_offset;
+	__s64 fractional_frequency_offset_ppt;
 };
 
 static inline struct dpll_pin_parent_device *
@@ -108,6 +110,13 @@ dpll_pin_parent_device_set_phase_offset(struct dpll_pin_parent_device *obj,
 	obj->_present.phase_offset = 1;
 	obj->phase_offset = phase_offset;
 }
+static inline void
+dpll_pin_parent_device_set_fractional_frequency_offset_ppt(struct dpll_pin_parent_device *obj,
+							   __s64 fractional_frequency_offset_ppt)
+{
+	obj->_present.fractional_frequency_offset_ppt = 1;
+	obj->fractional_frequency_offset_ppt = fractional_frequency_offset_ppt;
+}
 
 struct dpll_pin_parent_pin {
 	struct {
@@ -524,7 +533,6 @@ struct dpll_pin_get_rsp {
 		__u32 phase_adjust_max:1;
 		__u32 phase_adjust:1;
 		__u32 fractional_frequency_offset:1;
-		__u32 fractional_frequency_offset_ppt:1;
 		__u32 esync_frequency:1;
 		__u32 esync_pulse:1;
 		__u32 measured_frequency:1;
@@ -560,7 +568,6 @@ struct dpll_pin_get_rsp {
 	__s32 phase_adjust_max;
 	__s32 phase_adjust;
 	__s64 fractional_frequency_offset;
-	__s64 fractional_frequency_offset_ppt;
 	__u64 esync_frequency;
 	struct dpll_frequency_range *esync_frequency_supported;
 	__u32 esync_pulse;