diff --git a/tmp/ynl_build-tmp.VGVGm1/old-code/dpll-user.c b/tmp/ynl_build-tmp.VGVGm1/new-code/dpll-user.c
index 602f27ec93dc..c65a56e25aa1 100644
--- a/tmp/ynl_build-tmp.VGVGm1/old-code/dpll-user.c
+++ b/tmp/ynl_build-tmp.VGVGm1/new-code/dpll-user.c
@@ -145,6 +145,20 @@ const char *dpll_pin_state_str(enum dpll_pin_state value)
 	return dpll_pin_state_strmap[value];
 }
 
+static const char * const dpll_pin_operstate_strmap[] = {
+	[1] = "active",
+	[2] = "standby",
+	[3] = "no-signal",
+	[4] = "qual-failed",
+};
+
+const char *dpll_pin_operstate_str(enum dpll_pin_operstate value)
+{
+	if (value < 0 || value >= (int)YNL_ARRAY_SIZE(dpll_pin_operstate_strmap))
+		return NULL;
+	return dpll_pin_operstate_strmap[value];
+}
+
 static const char * const dpll_pin_capabilities_strmap[] = {
 	[0] = "direction-can-change",
 	[1] = "priority-can-change",
@@ -187,6 +201,7 @@ const struct ynl_policy_attr dpll_pin_parent_device_policy[DPLL_A_PIN_MAX + 1] =
 	[DPLL_A_PIN_DIRECTION] = { .name = "direction", .type = YNL_PT_U32, },
 	[DPLL_A_PIN_PRIO] = { .name = "prio", .type = YNL_PT_U32, },
 	[DPLL_A_PIN_STATE] = { .name = "state", .type = YNL_PT_U32, },
+	[DPLL_A_PIN_OPERSTATE] = { .name = "operstate", .type = YNL_PT_U32, },
 	[DPLL_A_PIN_PHASE_OFFSET] = { .name = "phase-offset", .type = YNL_PT_U64, },
 };
 
@@ -269,6 +284,7 @@ const struct ynl_policy_attr dpll_pin_policy[DPLL_A_PIN_MAX + 1] = {
 	[DPLL_A_PIN_PHASE_ADJUST_GRAN] = { .name = "phase-adjust-gran", .type = YNL_PT_U32, },
 	[DPLL_A_PIN_FRACTIONAL_FREQUENCY_OFFSET_PPT] = { .name = "fractional-frequency-offset-ppt", .type = YNL_PT_UINT, },
 	[DPLL_A_PIN_MEASURED_FREQUENCY] = { .name = "measured-frequency", .type = YNL_PT_U64, },
+	[DPLL_A_PIN_OPERSTATE] = { .name = "operstate", .type = YNL_PT_U32, },
 };
 
 const struct ynl_policy_nest dpll_pin_nest = {
@@ -324,6 +340,8 @@ int dpll_pin_parent_device_put(struct nlmsghdr *nlh, unsigned int attr_type,
 		ynl_attr_put_u32(nlh, DPLL_A_PIN_PRIO, obj->prio);
 	if (obj->_present.state)
 		ynl_attr_put_u32(nlh, DPLL_A_PIN_STATE, obj->state);
+	if (obj->_present.operstate)
+		ynl_attr_put_u32(nlh, DPLL_A_PIN_OPERSTATE, obj->operstate);
 	if (obj->_present.phase_offset)
 		ynl_attr_put_s64(nlh, DPLL_A_PIN_PHASE_OFFSET, obj->phase_offset);
 	ynl_attr_nest_end(nlh, nest);
@@ -360,6 +378,11 @@ int dpll_pin_parent_device_parse(struct ynl_parse_arg *yarg,
 				return YNL_PARSE_CB_ERROR;
 			dst->_present.state = 1;
 			dst->state = ynl_attr_get_u32(attr);
+		} else if (type == DPLL_A_PIN_OPERSTATE) {
+			if (ynl_attr_validate(yarg, attr))
+				return YNL_PARSE_CB_ERROR;
+			dst->_present.operstate = 1;
+			dst->operstate = ynl_attr_get_u32(attr);
 		} else if (type == DPLL_A_PIN_PHASE_OFFSET) {
 			if (ynl_attr_validate(yarg, attr))
 				return YNL_PARSE_CB_ERROR;
diff --git a/tmp/ynl_build-tmp.VGVGm1/old-code/dpll-user.h b/tmp/ynl_build-tmp.VGVGm1/new-code/dpll-user.h
index ac1f38633281..5123250e04b3 100644
--- a/tmp/ynl_build-tmp.VGVGm1/old-code/dpll-user.h
+++ b/tmp/ynl_build-tmp.VGVGm1/new-code/dpll-user.h
@@ -26,6 +26,7 @@ const char *dpll_type_str(enum dpll_type value);
 const char *dpll_pin_type_str(enum dpll_pin_type value);
 const char *dpll_pin_direction_str(enum dpll_pin_direction value);
 const char *dpll_pin_state_str(enum dpll_pin_state value);
+const char *dpll_pin_operstate_str(enum dpll_pin_operstate value);
 const char *dpll_pin_capabilities_str(enum dpll_pin_capabilities value);
 const char *dpll_feature_state_str(enum dpll_feature_state value);
 
@@ -46,6 +47,7 @@ struct dpll_pin_parent_device {
 		__u32 direction:1;
 		__u32 prio:1;
 		__u32 state:1;
+		__u32 operstate:1;
 		__u32 phase_offset:1;
 	} _present;
 
@@ -53,6 +55,7 @@ struct dpll_pin_parent_device {
 	enum dpll_pin_direction direction;
 	__u32 prio;
 	enum dpll_pin_state state;
+	enum dpll_pin_operstate operstate;
 	__s64 phase_offset;
 };
 
@@ -92,6 +95,13 @@ dpll_pin_parent_device_set_state(struct dpll_pin_parent_device *obj,
 	obj->state = state;
 }
 static inline void
+dpll_pin_parent_device_set_operstate(struct dpll_pin_parent_device *obj,
+				     enum dpll_pin_operstate operstate)
+{
+	obj->_present.operstate = 1;
+	obj->operstate = operstate;
+}
+static inline void
 dpll_pin_parent_device_set_phase_offset(struct dpll_pin_parent_device *obj,
 					__s64 phase_offset)
 {