diff --git a/tmp/ynl_build-tmp.COK3T5/old-code/dpll-user.c b/tmp/ynl_build-tmp.COK3T5/new-code/dpll-user.c
index 14011433d2d2..602f27ec93dc 100644
--- a/tmp/ynl_build-tmp.COK3T5/old-code/dpll-user.c
+++ b/tmp/ynl_build-tmp.COK3T5/new-code/dpll-user.c
@@ -229,6 +229,7 @@ const struct ynl_policy_attr dpll_policy[DPLL_A_MAX + 1] = {
 	[DPLL_A_CLOCK_QUALITY_LEVEL] = { .name = "clock-quality-level", .type = YNL_PT_U32, },
 	[DPLL_A_PHASE_OFFSET_MONITOR] = { .name = "phase-offset-monitor", .type = YNL_PT_U32, },
 	[DPLL_A_PHASE_OFFSET_AVG_FACTOR] = { .name = "phase-offset-avg-factor", .type = YNL_PT_U32, },
+	[DPLL_A_FREQUENCY_MONITOR] = { .name = "frequency-monitor", .type = YNL_PT_U32, },
 };
 
 const struct ynl_policy_nest dpll_nest = {
@@ -267,6 +268,7 @@ const struct ynl_policy_attr dpll_pin_policy[DPLL_A_PIN_MAX + 1] = {
 	[DPLL_A_PIN_REFERENCE_SYNC] = { .name = "reference-sync", .type = YNL_PT_NEST, .nest = &dpll_reference_sync_nest, },
 	[DPLL_A_PIN_PHASE_ADJUST_GRAN] = { .name = "phase-adjust-gran", .type = YNL_PT_U32, },
 	[DPLL_A_PIN_FRACTIONAL_FREQUENCY_OFFSET_PPT] = { .name = "fractional-frequency-offset-ppt", .type = YNL_PT_UINT, },
+	[DPLL_A_PIN_MEASURED_FREQUENCY] = { .name = "measured-frequency", .type = YNL_PT_U64, },
 };
 
 const struct ynl_policy_nest dpll_pin_nest = {
@@ -615,6 +617,11 @@ int dpll_device_get_rsp_parse(const struct nlmsghdr *nlh,
 				return YNL_PARSE_CB_ERROR;
 			dst->_present.phase_offset_avg_factor = 1;
 			dst->phase_offset_avg_factor = ynl_attr_get_u32(attr);
+		} else if (type == DPLL_A_FREQUENCY_MONITOR) {
+			if (ynl_attr_validate(yarg, attr))
+				return YNL_PARSE_CB_ERROR;
+			dst->_present.frequency_monitor = 1;
+			dst->frequency_monitor = ynl_attr_get_u32(attr);
 		}
 	}
 
@@ -739,6 +746,8 @@ int dpll_device_set(struct ynl_sock *ys, struct dpll_device_set_req *req)
 		ynl_attr_put_u32(nlh, DPLL_A_PHASE_OFFSET_MONITOR, req->phase_offset_monitor);
 	if (req->_present.phase_offset_avg_factor)
 		ynl_attr_put_u32(nlh, DPLL_A_PHASE_OFFSET_AVG_FACTOR, req->phase_offset_avg_factor);
+	if (req->_present.frequency_monitor)
+		ynl_attr_put_u32(nlh, DPLL_A_FREQUENCY_MONITOR, req->frequency_monitor);
 
 	err = ynl_exec(ys, nlh, &yrs);
 	if (err < 0)
@@ -1002,6 +1011,11 @@ int dpll_pin_get_rsp_parse(const struct nlmsghdr *nlh,
 			dst->esync_pulse = ynl_attr_get_u32(attr);
 		} else if (type == DPLL_A_PIN_REFERENCE_SYNC) {
 			n_reference_sync++;
+		} else if (type == DPLL_A_PIN_MEASURED_FREQUENCY) {
+			if (ynl_attr_validate(yarg, attr))
+				return YNL_PARSE_CB_ERROR;
+			dst->_present.measured_frequency = 1;
+			dst->measured_frequency = ynl_attr_get_u64(attr);
 		}
 	}
 
diff --git a/tmp/ynl_build-tmp.COK3T5/old-code/dpll-user.h b/tmp/ynl_build-tmp.COK3T5/new-code/dpll-user.h
index fc81c4937f03..ac1f38633281 100644
--- a/tmp/ynl_build-tmp.COK3T5/old-code/dpll-user.h
+++ b/tmp/ynl_build-tmp.COK3T5/new-code/dpll-user.h
@@ -262,6 +262,7 @@ struct dpll_device_get_rsp {
 		__u32 type:1;
 		__u32 phase_offset_monitor:1;
 		__u32 phase_offset_avg_factor:1;
+		__u32 frequency_monitor:1;
 	} _present;
 	struct {
 		__u32 module_name;
@@ -281,6 +282,7 @@ struct dpll_device_get_rsp {
 	enum dpll_type type;
 	enum dpll_feature_state phase_offset_monitor;
 	__u32 phase_offset_avg_factor;
+	enum dpll_feature_state frequency_monitor;
 };
 
 void dpll_device_get_rsp_free(struct dpll_device_get_rsp *rsp);
@@ -321,12 +323,14 @@ struct dpll_device_set_req {
 		__u32 mode:1;
 		__u32 phase_offset_monitor:1;
 		__u32 phase_offset_avg_factor:1;
+		__u32 frequency_monitor:1;
 	} _present;
 
 	__u32 id;
 	enum dpll_mode mode;
 	enum dpll_feature_state phase_offset_monitor;
 	__u32 phase_offset_avg_factor;
+	enum dpll_feature_state frequency_monitor;
 };
 
 static inline struct dpll_device_set_req *dpll_device_set_req_alloc(void)
@@ -362,6 +366,13 @@ dpll_device_set_req_set_phase_offset_avg_factor(struct dpll_device_set_req *req,
 	req->_present.phase_offset_avg_factor = 1;
 	req->phase_offset_avg_factor = phase_offset_avg_factor;
 }
+static inline void
+dpll_device_set_req_set_frequency_monitor(struct dpll_device_set_req *req,
+					  enum dpll_feature_state frequency_monitor)
+{
+	req->_present.frequency_monitor = 1;
+	req->frequency_monitor = frequency_monitor;
+}
 
 /*
  * Set attributes for a DPLL device
@@ -506,6 +517,7 @@ struct dpll_pin_get_rsp {
 		__u32 fractional_frequency_offset_ppt:1;
 		__u32 esync_frequency:1;
 		__u32 esync_pulse:1;
+		__u32 measured_frequency:1;
 	} _present;
 	struct {
 		__u32 module_name;
@@ -543,6 +555,7 @@ struct dpll_pin_get_rsp {
 	struct dpll_frequency_range *esync_frequency_supported;
 	__u32 esync_pulse;
 	struct dpll_reference_sync *reference_sync;
+	__u64 measured_frequency;
 };
 
 void dpll_pin_get_rsp_free(struct dpll_pin_get_rsp *rsp);