diff --git a/tmp/ynl_build-tmp.FdU9XC/old-code/dpll-user.c b/tmp/ynl_build-tmp.FdU9XC/new-code/dpll-user.c
index a1e6f55aa65f..14011433d2d2 100644
--- a/tmp/ynl_build-tmp.FdU9XC/old-code/dpll-user.c
+++ b/tmp/ynl_build-tmp.FdU9XC/new-code/dpll-user.c
@@ -266,6 +266,7 @@ const struct ynl_policy_attr dpll_pin_policy[DPLL_A_PIN_MAX + 1] = {
 	[DPLL_A_PIN_ESYNC_PULSE] = { .name = "esync-pulse", .type = YNL_PT_U32, },
 	[DPLL_A_PIN_REFERENCE_SYNC] = { .name = "reference-sync", .type = YNL_PT_NEST, .nest = &dpll_reference_sync_nest, },
 	[DPLL_A_PIN_PHASE_ADJUST_GRAN] = { .name = "phase-adjust-gran", .type = YNL_PT_U32, },
+	[DPLL_A_PIN_FRACTIONAL_FREQUENCY_OFFSET_PPT] = { .name = "fractional-frequency-offset-ppt", .type = YNL_PT_UINT, },
 };
 
 const struct ynl_policy_nest dpll_pin_nest = {
@@ -982,6 +983,11 @@ int dpll_pin_get_rsp_parse(const struct nlmsghdr *nlh,
 				return YNL_PARSE_CB_ERROR;
 			dst->_present.fractional_frequency_offset = 1;
 			dst->fractional_frequency_offset = ynl_attr_get_sint(attr);
+		} else if (type == DPLL_A_PIN_FRACTIONAL_FREQUENCY_OFFSET_PPT) {
+			if (ynl_attr_validate(yarg, attr))
+				return YNL_PARSE_CB_ERROR;
+			dst->_present.fractional_frequency_offset_ppt = 1;
+			dst->fractional_frequency_offset_ppt = ynl_attr_get_sint(attr);
 		} else if (type == DPLL_A_PIN_ESYNC_FREQUENCY) {
 			if (ynl_attr_validate(yarg, attr))
 				return YNL_PARSE_CB_ERROR;
diff --git a/tmp/ynl_build-tmp.FdU9XC/old-code/dpll-user.h b/tmp/ynl_build-tmp.FdU9XC/new-code/dpll-user.h
index fb497a033d1a..fc81c4937f03 100644
--- a/tmp/ynl_build-tmp.FdU9XC/old-code/dpll-user.h
+++ b/tmp/ynl_build-tmp.FdU9XC/new-code/dpll-user.h
@@ -503,6 +503,7 @@ struct dpll_pin_get_rsp {
 		__u32 phase_adjust_max:1;
 		__u32 phase_adjust:1;
 		__u32 fractional_frequency_offset:1;
+		__u32 fractional_frequency_offset_ppt:1;
 		__u32 esync_frequency:1;
 		__u32 esync_pulse:1;
 	} _present;
@@ -537,6 +538,7 @@ struct dpll_pin_get_rsp {
 	__s32 phase_adjust_max;
 	__s32 phase_adjust;
 	__s64 fractional_frequency_offset;
+	__s64 fractional_frequency_offset_ppt;
 	__u64 esync_frequency;
 	struct dpll_frequency_range *esync_frequency_supported;
 	__u32 esync_pulse;